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So, how to download this emu8086 program for free?
Article by: Glenn Posadas

This emu8086 is cool, better than NASM, MASM or TASM.
I used to program in TASM. I write my assembly language codes and assemble and run them in TASM.
You can write your program in any format, whether in TASM, NASM, MASM format, they are all compatible in emu8086.

Also, in emu8086, you can see the REAL and ACTUAL steps that an assemble does. It means that you can simulate every interrupts in your program :)

TO DOWNLOAD this emu8086:

STEP 1: CLICK HERE!
or if that link isn't working, visit the emu8086 official website: http://ziplib.com/emu8086/

STEP 2: INSTALL the program

STEP 3: insert this key, (NOTE THIS IS FROM http://www.serialportal.com/d.php) That site is cool. :) they give real keys. Thanks to them!


User:ISHAAN,glaitm    Key:27R3VDEFYFX4N0VC3FRTQZX
User:ISHAAN,glaitm    Key:27R3VDEFYFX4N0VC3FRTQZX

THEN VOILA!!!! IF you really want to help the developers of the emu8086 program, then buy your very OWN serial key from them! :)
-glenn


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APPENDIX C. INSTRUCTION SET AND INSTRUCTION TIMING OF 8086 Instruction Set of 8086 source: The X86 Microprocessors: Architecture and Programming (8086 to Pentium) In this table, the complete set of instructions of the 8086 has been listed, with their mnemonic and function. For knowing the details (format and examples) of each of the instruction, the section in the text book, where they are discussed is given in the third column of the table.

1. 2. Logical Instructions

      Mnemonic	Function	Section	Table
      NOT	Logical NOT of byte or word (one's complement)	—	3.7
      AND	Logical AND of byte or word	—	3.7
      OR	Logical OR of byte or word	—	3.7
      XOR	Logical exclusive – OR of byte or word	—	3.7
      TEST	Test byte or word (AND without storing)	—	3.7

      
      

      Shift and Rotate Instructions

      Mnemonic	Function	Section	Table
      SHL, SHR	Logical shift left, right byte or word by 1 or CL	3.6.1	3.8
      SAL, SAR	Arithmetic shift left, right byte or word by 1 or CL	4.7.3	3.8
      ROL, ROR	Rotate left, right, byte or word by 1 or CL	3.6.2	3.8
      RCL, RCR	Rotate left, right, through carry, byte or word by 1 or CL	3.6.2	3.8

      
      

      Arithmetic Instructions

      Mnemonic	Function	Section	Table
      ADD	Add byte or word	3.4.2	3.4
      SUB	Subtract byte or word	3.4.3	3.4
      ADC	Add byte or word and carry	3.4.2	3.4
      SBB	Subtract byte or word and carry (borrow)	3.4.3	3.4
      INC	Increment byte or word	3.4.2	3.4
      DEC	Decrement byte or word	3.4.3	3.4
      NEG	Negate byte or word (two's complement)	—	3.4
      CMP	Compare byte or word (subtract without storing)	3.4.4	3.4
      MUL	Multiply byte or word (unsigned)	3.4.5	3.4
      DIV	Divide byte or word (unsigned)	3.4.6	3.4
      IMUL	Integer multiply byte or word (signed)	4.7.2	3.4
      IDIV	Integer divide byte or word (signed)	4.7.2	3.4
      CBW, CWD	Convert byte to word, word to double word	4.7	3.4
      AAA	ASCII adjust for addition	4.5.1	3.4
      AAS	ASCII adjust for subtraction	4.5.2	3.4
      AAM	ASCII adjust for multiplication	4.5.3	3.4
      AAD	ASCII adjust for division	4.5.3	3.4
      DAA, DAS	Decimal adjust for addition, subtraction (binary coded decimal numbers)	4.4.2	3.4

      
      

      Jump and Loop Instructions

      Mnemonic	Function	Section	Table
      JMP	Unconditional jump	3.3.1 and 3.3.2	—
      JA (JNBE)	Jump if above (not below or equal)	—	3.3
      JAE (JNB)	Jump if above or equal (not below)	—	3.3
      JB (JNAE)	Jump if below (not above or equal)	—	3.3
      JBE (JNA)	Jump if below or equal (not above)	—	3.3
      JE (JZ)	Jump if equal (zero)	—	3.3
      JG (JNLE)	Jump if greater (not less or equal)	—	4.2
      JGE (JNL)	Jump if greater or equal (not less)	—	4.2
      JL (JNGE)	Jump if less (not greater nor equal)	—	4.2
      JLE (JNG)	Jump if less or equal (not greater)	—	4.2
      JC, JNC	Jump if carry set, carry not set	—	3.3
      JO, JNO	Jump if overflow, no overflow	—	4.2
      JS, JNS	Jump if sign, no sign	—	4.2
      JNP (JPO)	Jump if no parity (parity odd)	—	3.3
      JP (JPE)	Jump if parity (parity even)	—	3.3
      LOOP	Loop unconditional, count in CX	3.3.3	—
      LOOPE (LOOPZ)	Loop if equal (zero), count in CX	3.3.3	—
      LOOPNE (LOOPNZ)	Loop if not equal (not zero), count in CX	3.3.3	—
      JCXZ	Jump if CX equals zero	—	3.3

      
      

      Call and Return Instructions

      Mnemonic	Function	Section	Table
      CALL, RET	Call, return from procedure	4.2.2 and 4.2.3	—
      INT, INTO	Software interrupt, interrupt if overflow	8.3 and 8.2.5	—
      IRET	Return from interrupt	8.1.1	—

      
      

      String Instructions

      Mnemonic	Function	Section	Table
      MOVS	Move byte or word string	4.1.1	4.1
      CMPS	Compare byte or word string	4.1.2	4.1
      SCAS	Scan byte or word string	4.1.3	4.1
      LODS, STOS	Load, store byte or word string	4.1.4	4.1
      REP	Repeat	—	4.1
      REPE, REPZ	Repeat while equal, zero	—	4.1
      REPNE, REPNZ	Repeat while not equal (not zero)	—	4.1

      
      

      Processor and Flag Control Instructions

      Mnemonic	Function	Section	Table
      STC, CLC, CMC	Set, clear, complement carry flag	3.4.1	—
      STD, CLD	Set, clear direction flag	—	4.1
      STI, CLI	Set, clear interrupt enable flag	—	—
      LAHF, SAHF	Load AH from flags, store AH into flags	—	3.1
      PUSHF, POPF	Push flags onto stack, pop flags off stack	—	3.1
      ESC	Escape to external processor interface	13.2.1	—
      LOCK	Lock bus during next instruction	6.4.4	—
      NOP	No operation (do nothing)	6.5.1	—
      WAIT	Wait for signal on TEST input	13.2.1	—
      HLT	Halt processor	6.3.5	—
   3. Instruction Timing of 8086

      1. Number of cycles expended in calculating the 'Effective Address'

         No.	Addressing mode	No. of clocks for calculation of EA
         1	Direct	6
         2	Register indirect	5
         3	Register relative	9
         4	Based indexed with BP as the base register	8
         5	Based indexed with BX as the base register	7
         6	Relative based indexed with BP as the base register	12
         7	Relative based indexed with BX as the base register	11
      2. Number of clock cycles expended for each instruction of 8086

         Code	Description	8086
         AAA	ASCII adjust for addition	8
         AAD	ASCII adjust for division	60
         AAM	ASCII adjust for multiplication	83
         AAS	ASCII adjust for subtraction	8
         ADC	Add with carry
         	reg to reg	3
         	mem to reg	9+EA
         	reg to mem	16+EA
         	immed to reg	4
         	immed to mem	17+EA
         	immed to acc	4
         ADD	Addition
         	reg to reg	3
         	mem to reg	9+EA
         	reg to mem	16+EA
         	immed to reg	4
         	immed to mem	17+EA
         	immed to acc	4
         AND	Logical AND
         	reg to reg	3
         	mem to reg	9+EA
         	reg to mem	16+EA
         	immed to reg	4
         	immed to mem	17+EA
         	immed to acc	4
         CALL	Call a procedure
         	intrasegment direct	19
         	intrasegment direct
         	through register	16
         	intrasegment direct
         	through memory	21+EA
         	intrasegment direct	28
         CBW	Convert byte to word	2
         CLC	Clear carry flag	2
         CLD	Clear direction flag	2
         CLI	Clear interrupt flag	2
         CMC	Complement carry flag	2
         CMP	Compare
         	reg to reg	3
         	mem to mem	9+EA
         	reg to mem	9+EA
         	immed to reg	4
         	immed to mem	10+EA
         	immed to acc	4
         CMPS/	Compare string/
         CMPSB/	Compare byte string/
         CMPSW	Compare word string
         	Not repeated	22
         	REPE/REPNE CMPS/CMPSB/CMPSW	9+22/rep
         CWD	Convert word to doubleword	5
         DAA	Decimal adjust for addition	4
         DAS	Decimal adjust for subtraction	4
         DEC	Decrement by 1
         	16-bit reg	3
         	8-bit reg	3
         	memory	15+EA
         DIV	Unsigned division
         	8-bit reg	80–90
         	16-bit reg	144–162
         	8-bit mem	(86–96)+EA
         	16-bit mem	(150–168)+EA
         ESC	Escape
         	reg	2
         	mem	8+EA
         HLT	Halt	2
         IDIV	Integer division
         	8-bit reg	101–112
         	16-bit reg	165–184
         	8-bit mem	(107–118)+EA
         	16-bit mem	(171–190)+EA
         IMUL	Integer multiplication
         	8-bit reg	80–98
         	16-bit reg	128–154
         	8-bit mem	(86–104)+EA
         	16-bit mem	(134–160)+EA
         IN	Input from I /O port
         	Fixed port	10
         	Variable port through DX	8
         INC	Increment by 1
         	16-bit reg	3
         	8-bit reg	3
         	mem	15+EA
         INT	Interrupt
         	type=3	52
         	type3	51
         INTO	Interrupt if overflow
         	interrupt taken	53
         	interrupt not taken	4
         IRET	Return from interrupt	32
         JA /	Jump if above /	16, noj 4
         JNBE	Jump if not below or equal
         JAE /	Jump if above or equal	16, noj 4
         JNB	Jump if not below/
         JNA	Jump if not above
         JCXZ	Jump if CX is Zero	18, noj 6
         JE/	Jump if equal /	16, noj 4
         JZ	Jump if Zero
         JG/	Jump if greater	16, noj 4
         JNLE	Jump if not less, or equal
         JGE/	Jump if greater or equal /	16, noj 4
         JNL	Jump if not less
         JL /	Jump if less/	16, noj 4
         JNGE	Jump if not greater, or equal
         JLE/	Jump if less or equal /	16, noj 4
         JNG	Jump if not greater
         JMP	Jump
         	intrasegment direct short	15
         	intrasegment direct	15
         	intersegment direct	15
         	intrasegment indirect
         	through memory	18+EA
         	intrasegment indirect
         	through register	11
         	intrasegment indirect	24+EA
         JNE/	Jump if not equal /	16, noj 4
         JNZ	Jump if not Zero
         JNO	Jump if not overflow	16, noj 4
         JNP/	Jump if not parity/	16, noj 4
         JPO	Jump if parity odd
         JNS	Jump if not sign	16, noj 4
         JO	Jump if overflow	16, noj 4
         JP/	Jump if parity/	16, noj 4
         JPE	Jump if parity even
         JS	Jump if sign	16, noj 4
         LAHF	Load AH from flags	4
         LDS	Load pointer using DS/
         LES	Load pointer using ES	16+EA
         LEA	Load effective address	2+EA
         LOCK	Lock bus	2
         LODS/	Load string/
         LODSB	Load byte string
         LODSW	Load word string
         	not repeated	12
         	repeated	9+13/rep
         LOOP	Loop	17, noj 5
         LOOPE/	Loop if equal /
         LOOPZ	Loop if zero	18, noj 6
         LOOPNE /	Loop if not equal /
         LOOPNZ	Loop if not zero	19, noj 5
         MOV	Move
         	acc to mem	10
         	mem to acc	10
         	reg to reg	2
         	mem to reg	8+EA
         	reg to mem	9+EA
         	immed to reg	4
         	immed to mem	10+EA
         	reg to SS/DS/ES	2
         	mem to SS /DS /ES	8+EA
         	segment reg to reg	2
         	segment reg to mem	9+EA
         MOVS/	Move string /
         MOVSB/	Move byte string/
         MOVSW	Move word string
         	Not repeated	18
         	REP MOVS/MOVSB/MOVSW	9+17/rep
         MUL	Unsigned multiplication
         	8-bit reg	70–77
         	16-bit reg	118–133
         	8-bit mem	(76–83)+EA
         	16-bit mem	(124–139)+EA
         NEG	Negate
         	reg	3
         	mem	16+EA
         NOP	No operation	3
         NOT	Logical NOT
         	reg	3
         	mem	16+EA
         OR	Logical OR
         	reg to reg	3
         	mem to reg	9+EA
         	reg to mem	16+EA
         	immed to acc	4
         	immed to reg	4
         	immed to mem	17+EA
         OUT	Output to I /O port
         	fixed port	10
         	varible port	8
         POP	Pop word off stack
         	reg	8
         	segment reg	8
         	memory	17+EA
         POPF	Pop flags off stack	8
         PUSH	Push word onto stack
         	reg	11
         	segment reg:ES/SS/CS	10
         	memory	16+EA
         PUSHD	Push double flag onto stack	10
         RCL	Rotate left through carry /
         	Rotate right through carry /
         	reg with single-shift	2
         	reg with variable-shift	8+4 / bit
         	mem with single-shift	15+EA
         	mem with variable-shift	20+EA+4 / bnit
         RET	Return from procedure /
         RETF	Return far /
         RETN	Return near
         	intrasegment	16
         	intrasegment with constant	20
         	intrasegment	26
         	intrasegment with constant	25
         ROL/	Rotate left
         ROR	Rotate right
         	reg with single-shift	2
         	reg with variable-shift	8+4 / bit
         	mem with single-shift	15+EA
         	mem with variable-shift	20+EA+4 /bit
         SAHF	Store AH into flags	4
         SAL/	Shift arithmetic left /
         SAR /	Shift arithmetic right /
         SHL/	Shift logical left /
         SHR	Shift logical right
         	reg with single-shift	2
         	reg with variable-shift	8+4/ bit
         	mem with single-shift	15+EA
         	mem with variable shift	20+EA+4 / bit
         SBB	Subtract with borrow
         	reg from reg	3
         	mem from reg	9+EA
         	reg from mem	16+EA
         	immed from acc	4
         	immed from reg	4
         	immed from mem	17+EA
         SCAS/	Scan string /
         SCASB	Scan byte string
         SCASW	Scan word string
         	not repeated	15
         	REPE /REPNE SCAS /SCASB /SCASW	9+15/rep
         STC	Set carry flag	2
         STD	Set direction flag	2
         STI	Set interrupt flag	2
         STOS/	Store string /
         STOSB/	Store byte string /
         STOSW	Store word string
         	Not repeated	11
         	REP STOS/STOSB/STOSW	9+10/rep
         STR	Store task register
         SUB	Subtraction
         	reg from reg	3
         	mem from reg	9+EA
         	reg from mem	16+EA
         	immed from acc	4
         	immed from reg	4
         	immed from mem	17+EA
         TEST	Test
         	reg with reg	3
         	mem with reg	9+EA
         	immed with acc	4
         	immed with reg	5
         	immed with mem	11+EA
         WAIT	Wait while TEST pin
         	not asserted	4
         XADD	Exchange and add
         XCHG	Exchange
         	reg with acc	3
         	reg with mem	17+EA
         	reg with reg	4
         XLAT/	Translate	11
         XOR	Logical exclusive OR
         	reg with reg	3
         	mem with reg	9+EA
         	reg with mem	16+EA
         	immed with acc	4
         	immed with reg	4
         	immed with mem	17+EA

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